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copyright ? cirrus logic, inc. 2009 (all rights reserved) http://www.cirrus.com fractional-n clock multiplier features ? clock multiplier / jitter reduction ? generates a low jitter 6 - 75 mhz clock from a jittery or intermittent 50 hz to 30 mhz clock source ? highly accurate pll multiplication factor ? maximum error less than 1 ppm in high- resolution mode ? i2c? / spi? control port ? configurable auxiliary output ? flexible sourcing of reference clock ? external oscillator or clock source ? supports inexpensive local crystal ? minimal board space required ? no external analog loop-filter components general description the cs2100-cp is an extremely versatile system clocking device that utilizes a programmable phase lock loop. the cs2100-cp is based on a hybrid ana- log-digital pll architecture comprised of a unique combination of a delta-sigma fractional-n frequency synthesizer and a digital pll. this architecture allows for generation of a low-jitter clock relative to an exter- nal noisy synchronization clock at frequencies as low as 50 hz. the cs2100-cp supports both i2c and spi for full software control. the cs2100-cp is available in a 10-pin msop pack- age in commercial (-10c to +70c) grade. customer development kits are also available for device evalua- tion. please see ?ordering information? on page 32 for complete details. i2c / spi auxiliary output 6 to 75 mhz pll output 3.3 v i2c/spi software control 8 mhz to 75 mhz low-jitter timing reference fractional-n frequency synthesizer digital pll & fractional n logic output to input clock ratio n timing reference pll output lock indicator 50 hz to 30 mhz frequency reference frequency reference aug '09 ds840f1 cs2100-cp
cs2100-cp 2 ds840f1 table of contents 1. pin description ............................................................................................................ ..................... 4 2. typical connection diagram ................................................................................................. .... 5 3. characteristics and specificatio ns .......... ................. ................ ................ ................ ........... 6 recommended operating conditions .................................................................................... 6 absolute maximum rating s ............... ................. ................ ................ ............. ............. ............ .. 6 dc electrical characteristics ................................................................................................ 6 ac electrical characteristics ................................................................................................ 7 pll performance plots ......................................................................................................... ...... 8 control port switching characteristics- i2 c format ................................................... 9 control port switching characteristics - sp i format ............................................... 10 4. architecture overview ...................................................................................................... ....... 11 4.1 delta-sigma fractional-n fre quency synthesizer ......................................................................... 11 4.2 hybrid analog-digital phase locked loop ....... ............................................................................ .11 5. applications ............................................................................................................... .................... 13 5.1 timing reference clock input .............................................................................................. .......... 13 5.1.1 internal timing re ference clock divider ............................................................................... 13 5.1.2 crystal connections (xti and xto) ............ .......................................................................... 1 4 5.1.3 external reference clock (ref_clk) .................................................................................. 14 5.2 frequency reference clock in put, clk_in ................................................................................... 14 5.2.1 clk_in skipping mode .................................................................................................... ..... 14 5.2.2 adjusting the minimum loop bandwidth for cl k_in ............................................................ 16 5.3 output to input frequency ratio configuratio n ............................................................................. 17 5.3.1 user defined ratio (rud) ................................................................................................ ..... 17 5.3.2 ratio modifier (r-mod) .................................................................................................. ........ 18 5.3.3 effective ratio (reff) .................................................................................................. ........ 19 5.3.4 ratio configuration summary ..................... ........................................................................ .. 19 5.4 pll clock output .......................................................................................................... ................. 20 5.5 auxiliary output .......................................................................................................... .................... 20 5.6 clock output stability considerations ..................................................................................... ....... 21 5.6.1 output switching ........................................................................................................ ........... 21 5.6.2 pll unlock conditions ................................................................................................... ....... 21 5.7 required power up sequencing .............................................................................................. ...... 21 6. spi / i2c control port ..................................................................................................... .............. 21 6.1 spi control ............................................................................................................... ...................... 22 6.2 i2c control ............................................................................................................... ....................... 22 6.3 memory address pointer .................................................................................................... ........... 24 6.3.1 map auto increment ...................................................................................................... ........ 24 7. register quick reference ................................................................................................... ..... 24 8. register descriptions ...................................................................................................... .......... 25 8.1 device i.d. and revision (address 01h) ................................................................................... .... 25 8.1.1 device identification (device[4:0]) - read only ..................................................................... 25 8.1.2 device revision (revision[2:0]) - read only ........................................................................ 25 8.2 device control (address 02 h) .............................................................................................. .......... 25 8.2.1 unlock indicator (unlock) - read only .................................................................................. 2 5 8.2.2 auxiliary output disable (auxoutdis) ......... .......................................................................... 2 5 8.2.3 pll clock output disable (clkoutdis) ............ ...................................................................... 26 8.3 device configuration 1 (address 03h) ....................................................................................... .... 26 8.3.1 r-mod selection (rmodsel[2 :0]) .......................................................................................... .26 8.3.2 auxiliary output source selection (auxouts rc[1:0]) ............................................................. 26 8.3.3 enable device configuration registers 1 (e ndevcfg1) ........................................................ 27 8.4 global configuration (address 05h) ........................................................................................ ....... 27 8.4.1 device configuration free ze (freeze) ................................................................................ 27
cs2100-cp ds840f1 3 8.4.2 enable device configuration registers 2 (e ndevcfg2) ....................................................... 27 8.5 ratio (address 06h - 09h) ................................................................................................. ............. 27 8.6 function configuration 1 (address 16h) ..................................................................................... ... 28 8.6.1 clock skip enable (clksk ipen) ........................................................................................... .. 28 8.6.2 aux pll lock output config uration (auxlockcfg) .............................................................. 28 8.6.3 reference clock input divide r (refclkdiv[1:0]) .................................................................... 28 8.7 function configuration 2 (address 17h) ..................................................................................... ... 29 8.7.1 enable pll clock output on unlock (clkoutunl) ................................................................. 29 8.7.2 low-frequency ratio configuration (lfratiocfg) ................................................................ 29 8.8 function configuration 3 (address 1eh) ..................................................................................... ... 29 8.8.1 clock input bandwidth (clk in_bw[2:0]) ................................................................................ 29 9. calculating the user defined ratio .................................................................................... 30 9.1 high resolution 12.20 format .............................................................................................. ......... 30 9.2 high multiplication 20.12 format .......................................................................................... ......... 30 10. package dimensions ........................................................................................................ .......... 31 thermal characteristics ....................................................................................................... .. 31 11. ordering information ...................................................................................................... ........ 32 12. references ................................................................................................................ .................... 32 13. revision history .......................................................................................................... ................ 32 list of figures figure 1. typical connection diagram .......................................................................................... .............. 5 figure 2. clk_in sinusoidal jitt er tolerance .................................................................................. ........... 8 figure 3. clk_in sinusoidal jitter transfer ................................................................................... ............. 8 figure 4. clk_in random jitter re jection and tolerance ........................................................................ .8 figure 5. control port timing - i2c format .................................................................................... .............. 9 figure 6. control port timing - spi format (write only) ....................................................................... ... 10 figure 7. delta-sigma frac tional-n frequency synthesizer ..................................................................... 1 1 figure 8. hybrid analog-digital pll ................ ........................................................................... ............... 12 figure 9. internal timing reference clock divider ............................................................................. ...... 13 figure 10. ref_clk frequency vs a fixed clk_out ............................................................................ 13 figure 11. external component requir ements for crystal circu it ............................................................ 14 figure 12. clk_in removed for > 2 23 sysclk cycles ................................................................................ 15 figure 13. clk_in removed for < 2 23 sysclk cycles but > t cs .................................................................................. 15 figure 14. clk_in removed for < t cs ............................................................................................................................ ...... 16 figure 15. low bandwidth and new clock domain ................................................................................. ... 17 figure 16. high bandwi dth with clk_in domain re-use ........... ................................................................ 17 figure 17. ratio feature summary .............................................................................................. ............. 19 figure 18. pll clock output options ........................................................................................... ............ 20 figure 19. auxiliary output sele ction ......................................................................................... ............... 20 figure 20. control port timing in spi mode ...... .............................................................................. ......... 22 figure 21. control port timing, i2c write ..................................................................................... ............. 23 figure 22. control port timing, i2c aborted write + read ...................................................................... .23 list of tables table 1. ratio modifier ....................................................................................................... ....................... 18 table 2. example 12.20 r-values ............................................................................................... ............. 30 table 3. example 20.12 r-values ............................................................................................... ............. 30
cs2100-cp 4 ds840f1 1. pin description pin name # pin description vd 1 digital power ( input ) - positive power supply for the digital and analog sections. gnd 2 ground ( input ) - ground reference. clk_out 3 pll clock output ( output ) - pll clock output. aux_out 4 auxiliary output ( output ) - this pin outputs a buffered version of one of the input or output clocks, or a status signal, depending on register configuration. clk_in 5 frequency reference clock input ( input ) - clock input for the digital pll frequency reference. xto xti/ref_clk 6 7 crystal connections (xti/xto) / timing reference clock input (ref_clk) ( input/output ) - xti/xto are i/o pins for an external crystal whic h may be used to generate the low-jitter pll input clock. ref_clk is an input for an externa lly generated low-jitter reference clock. ad0/cs 8 address bit 0 (i2c) / contro l port chip select (spi) ( input ) - ad0 is a chip address pin in i2c mode. cs is the chip select signal in spi mode. scl/cclk 9 control port clock (input) - scl/cclk is the serial clock for the serial control port in i2c and spi mode. sda/cdin 10 serial control data ( input/output ) - sda is the data i/o line in i2c mode. cdin is the input data line for the control port interface in spi mode. 1 2 3 4 5 6 7 8 9 10 xto clk_out gnd vd xti/ref_clk ad0/cs scl/cclk sda/cdin aux_out clk_in
cs2100-cp ds840f1 5 2. typical connec tion diagram 2 1 gnd scl/cclk sda/cdin 2 k xti/ref_clk frequency reference clk_in xto clk_out aux_out 0.1 f vd +3.3 v notes : 1. resistors required for i 2 c operation. 2 k ad0/cs low-jitter timing reference system microcontroller 1 f note 1 1 or 2 ref_clk xto xti xto or 40 pf x 40 pf crystal to circuitry which requires a low-jitter clock n.c. to other circuitry or microcontroller figure 1. typical connection diagram cs2100-cp
cs2100-cp 6 ds840f1 3. characteristics an d specifications recommended operating conditions gnd = 0 v; all voltages with respect to ground. ( note 1 ) notes: 1. device functionality is not guaranteed or implied ou tside of these limits. operat ion outside of these limits may adversely affect device reliability. absolute maximum ratings gnd = 0 v; all voltages with respect to ground. warning: operation at or beyond these limits may result in permanent damage to the device. notes: 2. the maximum over/under voltage is limited by the input current except on the power supply pin. dc electrical characteristics test conditions (unless otherwise specified): vd = 3.1 v to 3.5 v; t a = -10c to +70c (commercial grade). notes: 3. to calculate the additional curr ent consumption due to loading (per output pin), multiply clock output frequency by load capacitance and power supply voltage. for example, f clk_out (49.152 mhz) * c l (15 pf) * vd (3.3 v) = 2.4 ma of additional current due to these loading conditions on clk_out. parameters symbol min typ max units dc power supply vd 3.1 3.3 3.5 v ambient operating temper ature (power applied) commercial grade t ac -10 - +70 c parameters symb ol min max units dc power supply vd -0.3 6.0 v input current i in -10ma digital input voltage ( note 2 )v in -0.3 vd + 0.4 v ambient operating temper ature (power applied) t a -55 125 c storage temperature t stg -65 150 c parameters symbol min typ max units power supply current - unloaded ( note 3 )i d -1218ma power dissipation - unloaded ( note 3 )p d -4060mw input leakage current i in --10a input capacitance i c -8-pf high-level input voltage v ih 70% - - vd low-level input voltage v il --30%vd high-level output voltage (i oh = -1.2 ma) v oh 80% - - vd low-level output voltage (i oh = 1.2 ma) v ol --20%vd
cs2100-cp ds840f1 7 ac electrical characteristics test conditions (unless otherwise sp ecified): vd = 3.1 v to 3.5 v; t a = -10c to +70c (commercial grade); c l =15pf. notes: 4. 1 ui (unit interval) corresponds to t sys_clk or 1/f sys_clk . 5. t cs represents the time from the removal of clk_in by which clk_in must be re-applied to ensure that pll_out continues while the pll re-acquires lock. this timeout is based on the internal vco frequen- cy, with the minimum timeout o ccurring at the maximum vco freq uency. lower vco frequencies will result in larger values of t cs . 6. only valid in cloc k skipping mode; see ?clk_in skipping mode? on page 14 for more information. 7. f clk_out = 24.576 mhz; sample size = 10,000 points; auxoutsrc[1:0] =11. 8. in accordance with aes-12id-2006 section 3.4.2. measurements are time interv al error taken with 3rd order 100 hz to 40 khz bandpass filter. 9. in accordance with aes-12id-2006 section 3.4.1. measurements are time interv al error taken with 3rd order 100 hz highpass filter. 10. 1 ui (unit interval) corresponds to t clk_in or 1/f clk_in . 11. the frequency accuracy of the pll clock output is di rectly proportional to the frequency accuracy of the reference clock. parameters symbol conditions min typ max units crystal frequency fundamental mode xtal f xtal refclkdiv[1:0] = 10 refclkdiv[1:0] = 01 refclkdiv[1:0] = 00 8 16 32 - - - 18.75 37.5 50 mhz mhz mhz reference clock input frequency f ref_clk refclkdiv[1:0] = 10 refclkdiv[1:0] = 01 refclkdiv[1:0] = 00 8 16 32 - - - 18.75 37.5 75 mhz mhz mhz reference clock input duty cycle d ref_clk 45 - 55 % internal system clock frequency f sys_clk 8 18.75 mhz clock input frequency f clk_in 50 hz - 30 mhz clock input pulse width ( note 4 )pw clk_in f clk_in < f sys_clk /96 f clk_in > f sys_clk /96 2 10 - - - - ui ns clock skipping timeout t cs (notes 5 , 6 )20--ms clock skipping input frequency f clk_skip ( note 6 ) 50 hz - 80 khz pll clock output frequency f clk_out 6-75mhz pll clock output duty cycle t od measured at vd/2 45 50 55 % clock output rise time t or 20% to 80% of vd - 1.7 3.0 ns clock output fall time t of 80% to 20% of vd - 1.7 3.0 ns period jitter t jit ( note 7 ) - 70 - ps rms base band jitter (100 hz to 40 khz) (notes 7 , 8 ) - 50 - ps rms wide band jitter (100 hz corner) (notes 7 , 9 ) - 175 - ps rms pll lock time - clk_in ( note 10 )t lc f clk_in < 200 khz f clk_in > 200 khz - - 100 1 200 3 ui ms pll lock time - ref_clk t lr f ref_clk = 8 to 75 mhz - 1 3 ms output frequency synthesis resolution ( note 11 )f err high resolution high multiplication 0 0 - - 0.5 112 ppm ppm
cs2100-cp 8 ds840f1 pll performance plots test conditions (unless otherwise specified): vd = 3.3 v; t a = 25 c (commercial grade); c l =15pf; f clk_out = 12.288 mhz; f clk_in = 12.288 mhz; sample size = 10,000 points; ba se band jitter (100 hz to 40 khz); auxoutsrc[1:0] =11. 1 10 100 1,000 10,000 0.1 1 10 100 1,000 10,000 input jitter frequency (hz) max input jitter level (usec) 1 hz bandwidth 128 hz bandwidth 1 10 100 1000 10000 -60 -50 -40 -30 -20 -10 0 10 input jitter frequency (hz) jitter transfer (db) 1 hz bandwidth 128 hz bandwidth figure 2. clk_in sinusoidal jitter toleranc e figure 3. clk_in sinusoidal jitter transfer samples size = 2.5m points; base band jitter (10hz to 40khz). samples size = 2.5m points; base band jitter (10hz to 40khz). figure 4. clk_in random jitter rejection and tolerance 0.01 0.1 1 10 100 1000 0.01 0.1 1 10 100 1000 input jitter level (nsec) output jitter level (nsec) 1 hz bandwidth 128 hz bandwidth unlock unlock
cs2100-cp ds840f1 9 control port switching cha racteristics- i2c format inputs: logic 0 = gnd; logic 1 = vd; c l =20pf. notes: 12. data must be held for sufficient ti me to bridge the transition time, t f , of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz bus free-time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling ( note 12 )t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t r -1s fall time scl and sda t f - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns delay from supply voltage stable to control port ready t dpor 100 - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl vd t dpor figure 5. control port timing - i2c format
cs2100-cp 10 ds840f1 control port switching cha racteristics - spi format inputs: logic 0 = gnd; logic 1 = vd; c l =20pf. notes: 13. t spi is only needed before first falling edge of cs after power is applied. t spi = 0 at all other times. 14. data must be held for sufficient time to bridge the transition time of cclk. 15. for f cclk < 1 mhz. parameter symbol min max unit cclk clock frequency f ccllk -6mhz cclk edge to cs falling ( note 13 )t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time ( note 14 )t dh 15 - ns rise time of cclk and cdin ( note 15 )t r2 - 100 ns fall time of cclk and cdin ( note 15 )t f2 - 100 ns delay from supply voltage stable to control port ready t dpor 100 - s t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t dpor vd figure 6. control port timing - spi format (write only)
cs2100-cp ds840f1 11 4. architecture overview 4.1 delta-sigma fractional- n frequency synthesizer the core of the cs2100 is a delta-sigma fractional-n frequency synthesizer which has very high-resolu- tion for input/output cloc k ratios, low phase noise, very wide ran ge of output frequencies and the ability to quickly tune to a new frequency. in very simplistic te rms, the fractional-n frequency synthesizer multiplies the timing reference clock by the value of n to generate the pll out put clock. the desired output to input clock ratio is the value of n that is a pplied to the delta-sigma modulator (see figure 7 ). the analog pll based frequency synthesizer uses a low-jitter timing reference clock as a time and phase reference for the inte rnal voltage controlled oscilla tor (vco). the phase compar ator compares the fraction- al-n divided clock with the original timing reference and generates a control signal. the control signal is fil- tered by the internal loop filter to generate the vco?s control voltage wh ich sets its output frequency. the delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio between the reference clock and the vco output (thus the one?s dens ity of the modulator sets the fractional value). this allows the design to be optimized fo r very fast lock times for a wide range of output frequencies without the need for external filter components. as with any frac tional-n frequency synthe sizer the timing reference clock should be stable and jitter-free. figure 7. delta-sigma fractional-n frequency synthesizer 4.2 hybrid analog-digital phase locked loop the addition of the digital pll and fractional-n logic (shown in figure 8 ) to the fractional-n frequency synthesizer creates the hybrid analog-digital phase locked loop with many advantages over classical an- alog pll techniques. these advantages in clude the ability to operate over extremely wide frequency ranges without the need to change external loop filter comp onents while maintaining impr essive jitter reduction per- formance. in the hybrid architecture, the digital pll ca lculates the ratio of the pll output clock to the fre- quency reference and compares that to the desired rati o. the digital logic genera tes a value of n which is then applied to the fractional-n frequency synthesizer to generate the desired pll output frequency. notice that the frequency and phase of the timing reference signal do not affect the ou tput of the pll since the digital control loop will correc t for the pll output. a majo r advantage of the digital pll is the ease with which the loop filter bandwidth can be altered. the pll ba ndwidth is automatically set to a wide-bandwidth mode to quickly achieve lock and then reduced for optimal jitter rejection. fractional-n divider timing reference clock pll output voltage controlled oscillator internal loop filter phase comparator n delta-sigma modulator
cs2100-cp 12 ds840f1 figure 8. hybrid analog-digital pll n digital filter frequency comparator for frac-n generation frequency reference clock delta-sigma fractional-n frequency synthesizer digital pll and fractional-n logic output to input ratio for hybrid mode fractional-n divider timing reference clock pll output voltage controlled oscillator internal loop filter phase comparator delta-sigma modulator
cs2100-cp ds840f1 13 5. applications 5.1 timing reference clock input the low jitter timing reference clock (refclk) can be pr ovided by either an external reference clock or an external crystal in conjunction with t he internal oscillator. in order to ma intain a stable and low-jitter pll out- put the timing reference clock must also be stable and low-jitter; the qu ality of the timing reference clock directly affects the performance of the pl l and hence the quality of the pll output. 5.1.1 internal timing reference clock divider the internal timing reference clock (sysclk) has a smaller maximum frequency than what is allowed on the xti/ref_clk pin. the cs2100 supports the wider external frequency range by offering an internal divider for refclk. the refclkdiv[1:0] bits should be set such that sy sclk, the divided refclk, then falls within the valid range as indicated in ?ac electrical characteristics? on page 7 . it should be noted that the maximum allowable in put frequency of the xti/ref_clk pin is dependent upon its configuration as either a crystal connection or external clock input. see the ?ac electrical char- acteristics? on page 7 for more details. for the lowest possible output jitter, attention should be paid to the absolute frequency of the timing ref- erence clock relative to the pll output frequency (c lk_out). to minimize outpu t jitter, the timing ref- erence clock frequency should be chosen such that f refclk is at least +/-15 khz from f clk_out *n/32 where n is an integer. figure 10 shows the effect of varying the refclk frequency around f clk_out *n/32. it should be noted that there will be a jitter null at the ze ro point when n = 32 (not shown in figure 10 ). an example of how to determine the range of refclk frequencies around 12 mhz to be used in order to achieve the lowest jitter pll output at a frequency of 12.288 mhz is as follows: where: and referenced control register location refclkdiv[1:0] ....................... ?reference clock input divider (refclkdiv[1:0])? on page 28 figure 9. internal timing reference clock divider n internal timing reference clock pll output fractional-n frequency synthesizer timing reference clock divider 1 2 4 xti/ref_clk refclkdiv[1:0] 8 mhz < sysclk < 18.75 mhz 8 mhz < refclk < timing reference clock 50 mhz (xti) 75 mhz (ref_clk) -80 -60 -40 -20 0 20 40 60 80 20 40 60 80 100 120 140 160 180 normalized ref__clk frequency (khz) typical base band jitter (psec) clk__out jitter -15 khz +15 khz clk__out f *32/n figure 10. ref_clk frequency vs a fixed clk_out f l f refclk f h ? f l f clk_out 31 32 ----- -15 khz + = 12.288 mhz 0.96875 15 khz + = 11.919 mhz = f h f clk_out 32 32 ----- -15 khz ? = 12.288 mhz 115 khz + = 12.273 mhz =
cs2100-cp 14 ds840f1 5.1.2 crystal connections (xti and xto) an external crystal may be used to generate refclk . to accomplish this, a 20 pf fundamental mode par- allel resonant crystal must be connected between the xti and xto pins as shown in figure 11 . as shown, nothing other than the crystal and its load capacitors should be connected to xti and xto. please refer to the ?ac electrical characteristics? on page 7 for the allowed crystal frequency range. 5.1.3 external reference clock (ref_clk) for operation with an externally generated ref_cl k signal, xti/ref_clk should be connected to the reference clock source and xto should be left unconnected or pulled low through a 47 k resistor to gnd. 5.2 frequency reference clock input, clk_in the frequency reference clock input (clk_in) is used by the digital pll and fractional-n logic block to dynamically generate a fractional-n va lue for the frequency synthesizer (see ?hybrid analog-digital pll? on page 12 ). the digital pll first compares the clk_in frequency to the pll output. the fractional-n logic block then translates the desired ratio based off of clk_in to one based off of the internal timing reference clock (sysclk). this allows the low-jitter timing refe rence clock to be used as the clock which the frequency synthesizer multiplies while maintaining synchronicity with the frequency reference clock through the digital pll. the allowable frequency range for clk_in is found in the ?ac electrical characteristics? on page 7 . 5.2.1 clk_in skipping mode clk_in skipping mode allows the pll to maintain lock even when the clk_in signal has missing pulses for up to 20 ms (t cs ) at a time (see ?ac electrical characteristics? on page 7 for specifications). clk_in skipping mode can only be used when the clk_in frequency is below 80 khz and clk_in is reapplied within 20 ms of being removed. the clkskipen bit enables this function. xti xto 40 pf 40 pf figure 11. external component requirement s for crystal circuit
cs2100-cp ds840f1 15 regardless of the setting of the clkskipen bit the pll output will continue for 2 23 sysclk cycles (466 ms to 1048 ms) after clk_in is removed (see figure 12 ). this is true as long as clk_in does not glitch or have an effective change in period as the clock sour ce is removed, otherwise the pll will interpret this as a change in frequency causing clock skipping and the 2 23 sysclk cycle time-out to be bypassed and the pll to immediately unlock. if the prior condit ions are met while clk_in is removed and 2 23 sysclk cycles pass, the pll will unlock and the pll_ou t state will be determined by the clkoutunl bit; see ?pll clock output? on page 20 . if clk_in is re-applied af ter such time, the pll will rema in unlocked for the specified time listed in the ?ac electrical characteristics? on page 7 after which lock will be acquired and the pll output will resume. if it is expected that clk_in will be removed and then reapplied within 2 23 sysclk cycles but later than t cs , the clkskipen bit should be disabled. if it is not disabled, the device will behave as shown in figure 13 ; note that the lower figure shows that the pll output frequency may change and be incorrect without an indication of an unlock condition. figure 12. clk_in removed for > 2 23 sysclk cycles clk_in pll_out unlock clkskipen =0 or 1 clkoutunl =0 lock time clk_in pll_out unlock clkskipen =0 or 1 clkoutunl =1 lock time = invalid clocks 2 23 sysclk cycles 2 23 sysclk cycles clk_in pll_out unlock clkskipen =0 or 1 clkoutunl =0 lock time clk_in pll_out unlock clkskipen =0 or 1 clkoutunl =1 lock time t cs t cs = invalid clocks clk_in pll_out unlock clkskipen = 1 clkoutunl =1 lock time t cs = invalid clocks 2 23 sysclk cycles 2 23 sysclk cycles 2 23 sysclk cycles figure 13. clk_in removed for < 2 23 sysclk cycles but > t cs
cs2100-cp 16 ds840f1 if clk_in is removed and then re-applied within t cs , the clkskipen bit determines whether pll_out continues while the pll re-acquires lock (see figure 14 ). when clkskipen is disabled and clk_in is re- moved the pll output will c ontinue until clk_in is re-a pplied at which point the pll will go unlocked only for the time it takes to acquire lock; th e pll_out state will be determined by the clkoutunl bit during this time. when clkskipen is enabled and clk_in is removed t he pll output clock will remain continuous throughout the missing clk_in period including the time while the pll re-acquires lock. 5.2.2 adjusting the minimum loop bandwidth for clk_in the cs2000 allows the minimum loop bandwidth of t he digital pll to be adjusted between 1 hz and 128 hz using the clkin_bw[2:0] bits. the minimum loop bandwidth of th e digital pll directly affects the jitter transfer function; specific ally, jitter frequencies below the loop bandwidth corner are passed from the pll input directly to the pll out put without attenuation. in some applications it is desirable to have a very low minimum loop bandwidth to reject ve ry low jitter frequencies, commonly referred to as wander. in others it may be preferable to remove only higher frequency jitter, allowing the input wa nder to pass through the pll without attenuation. referenced control register location clkskipen.............................. ?clock skip enable (clkskipen)? on page 28 clkoutunl.............................. ?enable pll clock output on unlock (clkoutunl)? on page 29 figure 14. clk_in removed for < t cs clk_in pll_out unlock clkskipen =1 clkoutunl =0 or 1 clk_in pll_out unlock clkskipen =0 clkoutunl =1 lock time clk_in pll_out unlock clkskipen =0 clkoutunl =0 lock time t cs t cs t cs = invalid clocks
cs2100-cp ds840f1 17 typically, applications in which the pll_out signal creates a new clock domain from which all other sys- tem clocks and associated data ar e derived will benefit from the maxi mum jitter and wander rejection of the lowest pll bandwidth setting. see figure 15 . systems in which some clocks and data are derived from the pll_out signal while other clocks and data are derived from the clk_in signal will often require phase alignment of all the clocks and data in the system. see figure 16 . if there is substantial wander on the clk_ in signal in these applications, it may be necessary to increase the minimum loop bandwid th allowing this wander to pass through to the clk_out signal in order to maintain phase alignment. for these applications, it is advised to experiment with the loop bandwidth settings and choose the lowest bandwidth setting that does not produce system timing errors due to wandering between the clocks and data synchronous to the clk_in domain and those synchronous to the pll_out domain. it should be noted that manual adjustment of the minimum loop bandwidth is not necessary to acquire lock; this adjustment is made autom atically by the digital pll. while acquiring lock, the digital loop band- width is automatically set to a large value. once lock is achiev ed, the digital loop bandwidth will settle to the minimum value selected by the clkin_bw[2:0] bits. 5.3 output to input freque ncy ratio configuration 5.3.1 user defined ratio (r ud ) the user defined ratio, r ud , is a 32-bit un-signed fixed-point number, stored in the ratio register set, which determines the basis fo r the desired input to output clock ratio. the 32-bit r ud can be expressed referenced control register location clkin_bw[2:0] ....................... ?clock input bandwidth (clkin_bw[2:0])? on page 29 figure 15. low bandwidt h and new clock domain lrck sclk sdata mclk mclk wander > 1 hz wander and jitter > 1 hz rejected d0 d1 lrck sclk sdata subclocks generated from new clock domain. or pll bw = 1 hz clk_in pll_out d0 d1 jitter figure 16. high bandwidth with clk_in domain re-use d0 d1 lrck sclk sdata mclk mclk wander < 128 hz jitter > 128 hz rejected wander < 128 hz passed to output lrck sclk sdata or pll bw = 128 hz clk_in pll_out subclocks and data re-used from previous clock domain. jitter d0 d1
cs2100-cp 18 ds840f1 in either a high resolution (12.20) or high mu ltiplication (20.12) form at selectable by the lfratiocfg bit, with 20.12 being the default. the r ud for high resolution (12.20) format is encoded with 12 msbs representing the integer binary por- tion with the remaining 20 lsbs representing the frac tional binary portion. the maximum multiplication factor is approximately 4096 with a resolution of 0.954 ppm in this configuration. see ?calculating the user defined ratio? on page 30 for more information. the r ud for high multiplication (20.12) format is encod ed with 20 msbs representing the integer binary portion with the remaining 12 lsbs representing the frac tional binary portion. in this configuration, the maximum multiplication factor is approximately 1,048,575 with a resolution of 244 ppm. it is recommend- ed that the 12.20 high-reso lution format be utilized whenever the desired ratio is less than 4096 since the output frequency accuracy of the pll is directly proportional to the accuracy of the timing reference clock and the resolution of the r ud . the status of internal dividers, such as the internal timing reference clock divider, are automatically taken into account. therefore r ud is simply the desired ratio of th e output to input clock frequencies. 5.3.2 ratio modifier (r-mod) the ratio modifier is used to internally multip ly/divide the r ud (the ratio stored in the register space re- mains unchanged). the available options for r mod are summarized in table 1 on page 18 . the r-mod value selected by rmodsel[2:0] is always used in the calculation for the effective ratio (r eff ), see ?effective ratio (reff)? on page 19 . if r-mod is not desired, rmodsel[2:0] should be left at its default value of ?000?, which corresponds to an r- mod value of 1, thereby effectively disabling the ratio modifier. table 1. ratio modifier referenced control register location ratio...................................... ?ratio (address 06h - 09h)? on page 27 lfratiocfg ............................ ?low-frequency ratio configuration (lfratiocfg)? on page 29 rmodsel[2:0] ratio modifier 000 1 001 2 010 4 011 8 100 0.5 101 0.25 110 0.125 111 0.0625 referenced control register location ratio...................................... ?ratio (address 06h - 09h)? on page 27 rmodsel[2:0] ........................ ?r-mod selection (rmodsel[2:0])? section on page 26
cs2100-cp ds840f1 19 5.3.3 effective ratio (r eff ) the effective ratio (r eff ) is an internal calculation comprised of r ud and the appropriate modifiers, as previously described. r eff is calculated as follows: r eff = r ud ? r mod to simplify operation the device handles some of th e ratio calculation functi ons automatically (such as when the internal timing reference clock divider is se t). for this reason, the ef fective ratio does not need to be altered to account for internal dividers. ratio modifiers which would produce an overflow or truncation of r eff should not be used; for example if r ud is 1024 an r mod of 8 would produce an r eff value of 8192 which exceeds the 4096 limit of the 12.20 format. in all cases, the maximum and minimum allowable values for r eff are dictated by the fre- quency limits for both the input and output clocks as shown in the ?ac electrical characteristics? on page 7 . 5.3.4 ratio configuration summary the r ud is the user defined ratio stored in the register space. the resolution for the r ud is selectable by setting lfratiocfg . r-mod is applied if selected. the user defi ned ratio, and ratio modifier make up the effective ratio r eff , the final calculation used to determine th e output to input clock ratio. the effective ratio is then corrected for the internal dividers. the conceptual diagram in figure 17 summarizes the fea- tures involved in the calculation of the ratio values used to generate the fractional-n value which controls the frequency synthesizer. figure 17. ratio feature summary referenced control register location ratio...................................... ?ratio (address 06h - 09h)? on page 27 lfratiocfg ............................ ?low-frequency ratio configuration (lfratiocfg)? on page 29 rmodsel[2:0] ........................ ?r-mod selection (rmodsel[2:0])? section on page 26 refclkdiv[1:0] ....................... ?reference clock input divider (refclkdiv[1:0])? on page 28 effective ratio r eff ratio format frequency reference clock (clk_in) sysclk pll output frequency synthesizer digital pll & fractional n logic n ratio 12.20 20.12 lfratiocfg rmodsel[2:0] ratio modifier r correction refclkdiv[1:0] timing reference clock (xti/ref_clk) divide refclkdiv[1:0] user defined ratio r ud
cs2100-cp 20 ds840f1 5.4 pll clock output the pll clock output pin (clk_out) provides a buffered version of the output of the frequency synthesizer. the driver can be set to high-impedance with the clkoutdis bit. the output from the pll automatically drives a static low condition while the pll is un-locked (when the clock may be unreliable). this feat ure can be disabled by setting the clkoutunl bit, however the state clk_out may then be unreliable during an unlock condition. figure 18. pll clock output options 5.5 auxiliary output the auxiliary output pin (aux_out ) can be mapped, as shown in figure 19 , to one of four signals: refer- ence clock (refclk), input clock (clk_i n), additional pll clock output (clk_out), or a pll lock indicator (lock). the mux is controlled via the auxoutsrc[1:0] bits. if aux_out is set to lock, the auxlockcfg bit is then used to control the output driver ty pe and polarity of the lock signal (see section 8.6.2 on page 28 ). if aux_out is set to clk_out the phase of the pl l clock output signal on aux_out may differ from the clk_out pin. the driver for the pin can be set to high-impedance using the auxoutdis bit. figure 19. auxiliary output selection referenced control register location clkoutunl.............................. ?enable pll clock output on unlock (clkoutunl)? on page 29 clkoutdis .............................. ?pll clock output disable (clkoutdis)? on page 26 referenced control register location auxoutsrc[1:0]...................... ?auxiliary output source selection (auxoutsrc[1:0])? on page 26 auxoutdis ............................. ?auxiliary output disable (auxoutdis)? on page 25 auxlockcfg........................... ?aux pll lock output configuration (auxlockcfg)? section on page 28 pll locked/unlocked pll output 2:1 mux clkoutdis 2:1 mux clkoutunl 0 pll clock output pin (clk_out) 0 1 0 1 pll clock output pllclkout frequency reference clock (clk_in) pll lock/unlock indication (lock) timing reference clock (refclk) pll clock output (pllclkout) 4:1 mux auxiliary output pin (aux_out) auxoutdis auxoutsrc[1:0] auxlockcfg
cs2100-cp ds840f1 21 5.6 clock output stability considerations 5.6.1 output switching cs2100 is designed such that re-configuration of the clock routing functions do not result in a partial clock period on any of the active outputs (clk_out and/or aux_out). in particular, enabling or disabling an output, changing the auxilia ry output source between ref_clk and clk_ou t, and the automatic dis- abling of the output(s) duri ng unlock will not cause a runt or partial clock period. the following exceptions/limitations exist: ? enabling/disabling aux_out when auxoutsrc[1:0] = 11 (unlock indicator). ? switching auxoutsrc[1:0] to or from 01 (pll clock input) and to or from 11 (unlock indicator) (transitions between auxoutsrc[1:0] = [00,10] will not produce a glitch). ? changing the clkoutunl bit while the pll is in operation. when any of these exceptions occur, a part ial clock period on the output may result. 5.6.2 pll unlock conditions certain changes to the cloc k inputs and registers can cause the pll to lose lock which will affect the pres- ence the clock signal on clk_out. the following outlines which conditions cause the pll to go un- locked: ? changes made to the registers which affect the fr action-n value that is us ed by the frequency syn- thesizer. this includes all the bits shown in figure 17 on page 19 . ? any discontinuities on the ti ming reference clock, ref_clk. ? discontinuities on the frequency reference clock, clk_in, except when the clock skipping feature is enabled and the requirements of clock skipping are satisfied (see ?clk_in skipping mode? on page 14 ). ? gradual changes in clk_in frequency great er than 30% from the starting frequency. ? step changes in clk_in frequency. 5.7 required power up sequencing ? apply power to the device. the output pins will remain low until the device is configured with a valid ratio via the control port. ? write the desired operational configurations. the endevcfg1 and endevcfg2 bits must be set to 1 dur- ing the initialization register writes; the order does not matter. ? the freeze bit may be set prior to this step and cleared afterward to ensure all settings take effect at the same time. 6. spi / i2c control port the control port is used to access the registers and allows the device to be configured for the desired operational modes and formats. the operation of t he control port may be completely asyn chronous with respect to device inputs and outputs. however, to avoi d potential interference problems, the control port pins should remain static if no op- eration is required.
cs2100-cp 22 ds840f1 the control port operates with either the spi or i2c interface, with the cs2100 acting as a slave device. spi mode is selected if there is a high-to-low transition on the ad0/cs pin after power-up. i2c mode is selected by connecting the ad0/cs pin through a resistor to vd or gnd, thereby pe rmanently selecting the desired ad0 bit address state. in both modes the endevcfg1 and endevcfg2 bits must be set to 1 for normal operation. warning: all ?reserved? registers must ma intain their default state to ensure proper functional operation. 6.1 spi control in spi mode, cs is the chip select signal; cclk is the contro l port bit clock (sourced from a microcontroller), and cdin is the input data line from the microcontroller. data is clocked in on the rising edge of cclk. the device only supports write operations. figure 20 shows the operation of the co ntrol port in spi mode. to write to a register, bring cs low. the first eight bits on cdin form the chip address and must be 10011110. the next eight bits form the memory ad- dress pointer (map), which is set to the address of the register that is to be upd ated. the next eight bits are the data which will be plac ed into the register designated by the map. there is map auto increment capability, enabled by the incr bit in the m ap register. if incr is a zero, the map will stay constant for successive read or writes. if incr is set to a 1, the map will automatically incre- ment after each byte is read or written, allowing block writes of successive registers. 6.2 i2c control in i2c mode, sda is a bidirectional dat a line. data is clocked into and ou t of the device by the clock, scl. there is no cs pin. the ad0 pin forms the least-significant bit of the chip address and should be connected to vd or gnd as appropriate. the state of the ad0 pin should be maintained throughout operation of the device. the signal timings for a read and write cycle are shown in figure 21 and figure 22 . a start condition is de- fined as a falling transition of sda while the clock is high. a stop conditi on is a rising transition while the clock is high. all other transitions of sda occur wh ile the clock is low. the first byte sent to the cs2100 after a start condition consists of the 7-bit chip address field and a r/w bit (high for a read, low for a write). the upper 6 bits of the 7-bit address field are fixed at 10 0111 followed by the logic state of the ad0 pin. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address point- er (map) which selects the register to be read or writt en. if the operation is a read, the contents of the reg- ister pointed to by the m ap will be output. setting the auto increment bit in map allows successive reads or writes of consecutive registers. each byte is separa ted by an acknowledge bit. the ack bit is output from the cs2100 after each input byte is read and is input from the microcontroller after each transmitted byte. referenced control register location endevcfg1 ............................ ?enable device configuration registers 1 (endevcfg1)? on page 27 endevcfg2 ............................ ?enable device configuration registers 2 (endevcfg2)? section on page 27 4 5 6 7 cclk chip address map byte data 1 0 0 1 1 1 1 0 cdin incr 6 5 4 3 2 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 10 11 13 14 15 data +n cs 7 6 1 0 figure 20. control port timing in spi mode
cs2100-cp ds840f1 23 since the read operation cannot set the map, an aborte d write operation is used as a preamble. as shown in figure 21 , the write operation is aborted after the acknowledge for the map byte by sending a stop con- dition. the following pseudocode illustrates an aborted wr ite operation followed by a read operation. send start condition. send 100111x0 (chip address & write operation). receive acknowledge bit. send map byte, auto increment off. receive acknowledge bit. send stop condition, aborting write. send start condition. send 100111x1(chip address & read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. setting the auto increment bit in th e map allows successive reads or wr ites of consecutiv e registers. each byte is separated by an acknowledge bit. 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 21. control port timing, i2c write scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 1 1 ad0 0 sda 1 0 0 1 1 1 ad0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 22. control port timing, i2c aborted write + read
cs2100-cp 24 ds840f1 6.3 memory address pointer the memory address pointer (map) byte comes after th e address byte and selects the register to be read or written. refer to the pseudocode above for implementation details. 6.3.1 map auto increment the device has map auto increment ca pability enabled by the incr bit (t he msb) of the map. if incr is set to 0, map will stay constant for successive i2c writes or reads and spi writes. if incr is set to 1, map will auto increment after each byte is read or written, allowing block reads or writes of successive regis- ters. 7. register qu ick reference this table shows the register and bit nam es with their associated default values. endevcfg1 and endevcfg2 bits must be set to 1 for normal operation. warning: all ?reserved? registers must ma intain their default state to ensure proper functional operation. adr name 7 6 5 4 3 2 1 0 01h device id device4 device3 device2 devic e1 device0 revision2 revision1 revision0 p25 00000 x xx 02h device ctrl unlock reserved reserved rese rved reserved reserved auxoutdis clkoutdis p25 xxx00000 03h device cfg 1 rmodsel2 rmodsel1 rmodsel0 reser ved reserved auxoutsrc1 auxoutsrc0 endevcfg1 p26 00000 0 00 05h global cfg reserved reserved reserved res erved freeze reserved reserved endevcfg2 p27 00000 0 00 06h - 09h 32-bit ratio msb ........................................................................................................................... m sb-7 msb-8 .......................................................................................................................... . msb-15 lsb+15 ......................................................................................................................... .. lsb+8 lsb+7 .......................................................................................................................... .lsb 16h funct cfg 1 clkskipen auxlockcfg reserved ref clkdiv1 refclkdiv0 reserved reserved reserved p28 00000 0 00 17h funct cfg 2 reserved reserved reserved clkoutunl lfratiocfg reserved reserved reserved p29 00000 0 00 1eh funct cfg 3 reserved clkin_bw2 clkin_bw1 clk in_bw0 reserved reserved reserved reserved p29 00000 0 00
cs2100-cp ds840f1 25 8. register descriptions in i2c mode all registers are read/write unless otherwise stated. in spi mode all registers are write only. all ?re- served? registers must maintain their default state to en sure proper functional operation. the default state of each bit after a power-up sequence or reset is indicated by the shaded row in the bit decode table and in the ?register quick reference? on page 24 . control port mode is entered when the device recognizes a va lid chip address input on it s i2c/spi serial control pins and the endevcfg1 and endevcfg2 bits are set to 1. 8.1 device i.d. and r evision (address 01h) 8.1.1 device identification (device[4:0]) - read only i.d. code for the cs2100. 8.1.2 device revision (revision[2:0]) - read only cs2100 revision level. 8.2 device control (address 02h) 8.2.1 unlock indicator (unlock) - read only indicates the lock state of the pll. 8.2.2 auxiliary output disable (auxoutdis) this bit controls the output driver for the aux_out pin. 76543210 device4 device3 device2 device1 device0 revision2 revision1 revision0 device[4:0] device 00000 cs2100. revid[2:0] revision level 100 b2 and b3 110 c1 76543210 unlock reserved reserved reserved reserved reserved auxoutdis clkoutdis unlock pll lock state 0 pll is locked. 1 pll is unlocked. auxoutdis output driver state 0 aux_out output driver enabled. 1 aux_out output driver set to high-impedance. application: ?auxiliary output? on page 20
cs2100-cp 26 ds840f1 8.2.3 pll clock output disable (clkoutdis) this bit controls the output driver for the clk_out pin. 8.3 device configuration 1 (address 03h) 8.3.1 r-mod selection (rmodsel[2:0]) selects the r-mod value, which is used as a fa ctor in determining the pll?s fractional n. 8.3.2 auxiliary output sour ce selection (auxoutsrc[1:0]) selects the source of the aux_out signal. note: when set to 11, auxlckcfg sets the polarity and driver type. see ?aux pll lock output config- uration (auxlockcfg)? on page 28 . clkoutdis output driver state 0 clk_out output driver enabled. 1 clk_out output driver set to high-impedance. application: ?pll clock output? on page 20 76543210 rmodsel2 rmodsel1 rmodsel0 reserved rese rved auxoutsrc1 auxo utsrc0 endevcfg1 rmodsel[2:0] r-mod selection 000 left-shift r-value by 0 (x 1). 001 left-shift r-value by 1 (x 2). 010 left-shift r-value by 2 (x 4). 011 left-shift r-value by 3 (x 8). 100 right-shift r-value by 1 ( 2). 101 right-shift r-value by 2 ( 4). 110 right-shift r-value by 3 ( 8). 111 right-shift r-value by 4 ( 16). application: ?ratio modifier (r-mod)? on page 18 auxoutsrc[1:0] auxiliary output source 00 refclk. 01 clk_in. 10 clk_out. 11 pll lock status indicator. application: ?auxiliary output? on page 20
cs2100-cp ds840f1 27 8.3.3 enable device configurat ion registers 1 (endevcfg1) this bit, in conjunction with endevcfg2 , configures the device for control port mode. these endevcfg bits can be set in any order and at any time during the control port access sequence, however they must both be set before normal operation can occur. note: endevcfg2 must also be set to enable control port mode. see ?spi / i2c co ntrol port? on page 21 . 8.4 global configur ation (address 05h) 8.4.1 device configurati on freeze (freeze) setting this bit allows writes to the device control and device config uration registers (address 02h - 04h) but keeps them from taking effe ct until this bit is cleared. 8.4.2 enable device configurat ion registers 2 (endevcfg2) this bit, in conjunction with endevcfg1 , configures the device for control port mode. these endevcfg bits can be set in any order and at any time during the control port access sequence, however they must both be set before normal operation can occur. note: endevcfg1 must also be set to enable control port mode. see ?spi / i2c co ntrol port? on page 21 . 8.5 ratio (address 06h - 09h) these registers contain the user defined ratio as shown in the ?register quick reference? section on page 24 . these 4 registers form a single 32-bit ratio value as shown above. see ?output to input frequency ratio configuration? on page 17 and ?calculating the user defined ratio? on page 30 for more details. endevcfg1 register state 0 disabled. 1 enabled. application: ?spi / i2c control port? on page 21 76543210 reserved reserved reserved reserved freeze reserved reserved endevcfg2 freeze device control and configuration registers 0 register changes take effect immediately. 1 modifications may be made to device control and device configuration registers (registers 02h-04h) without the changes taking effect until after the freeze bit is cleared. endevcfg2 register state 0 disabled. 1 enabled. application: ?spi / i2c control port? on page 21 76543210 msb ............................................................................................................................ ....................... msb-7 msb-8 .......................................................................................................................... ......................... msb-15 lsb+15 ......................................................................................................................... .......................... lsb+8 lsb+7 .......................................................................................................................... ......................... lsb
cs2100-cp 28 ds840f1 8.6 function configuration 1 (address 16h) 8.6.1 clock skip enable (clkskipen) this bit enables clock skipping mode for the pll and allows the pll to mainta in lock even when the clk_in has missing pulses. note: f clk_in must be < 80 khz and re-applied within 20 ms to use this feature. 8.6.2 aux pll lock output configuration (auxlockcfg) when the aux_out pin is configured as a lock indicator ( auxoutsrc[1:0] = 11), this bit configures the aux_out driver to either push-pull or open drain. it also determines the polarity of the lock signal. if aux_out is configured as a clock output, the state of this bit is disregarded. note: aux_out is an un lock indicator, signalling an error condition when the pll is unlocked. there- fore, the pin polarity is defined relative to the un lock condition. 8.6.3 reference clock input divider (refclkdiv[1:0]) selects the input divider for the timing reference clock. 76543210 clkskipen auxlockcfg reserved refclkdiv 1 refclkdiv0 reserved reserved reserved clkskipen pll clock skipping mode 0 disabled. 1 enabled. application: ?clk_in skipping mode? on page 14 auxlockcfg aux_out driver configuration 0 push-pull, active high (output ?high? for unlocked condition, ?low? for locked condition). 1 open drain, active low (output ?low? for unl ocked condition, high-z for locked condition). application: ?auxiliary output? on page 20 refclkdiv[1:0] reference clock input divider ref_clk frequency range 00 4. 32 mhz to 75 mhz (50 mhz with xti) 01 2. 16 mhz to 37.5 mhz 10 1. 8 mhz to 18.75 mhz 11 reserved. application: ?internal timing reference clock divider? on page 13
cs2100-cp ds840f1 29 8.7 function configuration 2 (address 17h) 8.7.1 enable pll clock out put on unlock (clkoutunl) defines the state of the pll output during the pll unlock condition. 8.7.2 low-frequency ratio configuration (lfratiocfg) determines how to interpret th e 32-bit user defined ratio. 8.8 function configuration 3 (address 1eh) 8.8.1 clock input bandwidth (clkin_bw[2:0]) sets the minimum loop bandwidth when locked to clk_in. note: in order to guarantee that a change in minimum bandwidth takes effect, t hese bits must be set prior to acquiring lock (removing and re-applying clk_in can provide the unlock condit ion necessary to initiate the setting change). in pr oduction systems these bits should be configured with the desired values prior to setting the endevcfg bits; this guarantees that the setting takes effect prior to acquiring lock. 76543210 reserved reserved reserved clkoutunl lfratiocfg reserved reserved reserved clkoutunl clock output enable status 0 clock outputs are driven ?low? when pll is unlocked. 1 clock outputs are always enabled (results in unpredictable output when pll is unlocked). application: ?pll clock output? on page 20 lfratiocfg ratio bit encoding interpretation 0 20.12 - high multiplier. 1 12.20 - high accuracy. application: ?user defined ratio (rud)? on page 17 76543210 reserved clkin_bw2 clkin_bw1 clkin_bw0 reserved reserved reserved reserved clkin_bw[2:0] minimum loop bandwidth 000 1 hz 001 2 hz 010 4 hz 011 8 hz 100 16 hz 101 32 hz 110 64 hz 111 128 hz application: ?adjusting the minimum loop bandwidth for clk_in? on page 16
cs2100-cp 30 ds840f1 9. calculating the us er defined ratio note: the software for use with the evaluation kit has built in tools to aid in calculating and converting the user defined ratio. this section is for those who are not in terested in the software or who are developing their systems without the aid of the evaluation kit. most calculators do not interpret the fixed point binary representation which the cs2100 uses to define the output to input clock ratio (see section 5.3.1 on page 17 ); however, with a simple conver sion we can use these tools to generate a binary or hex value which can be written to the ratio register. 9.1 high resolution 12.20 format to calculate the user defined ratio (r ud ) to store in the register(s), divi de the desired output clock frequen- cy by the given input clock (clk_in). then multip ly the desired ratio by the scaling factor of 2 20 to get the scaled decimal representation; then use the decimal to binary /hex conversion function on a calculator and write to the register. a few examples have been provided in table 2 . table 2. example 12.20 r-values 9.2 high multiplication 20.12 format to calculate the user defined ratio (r ud ) to store in the register(s), divi de the desired output clock frequen- cy by the given input clock (clk_in). then multip ly the desired ratio by the scaling factor of 2 12 to get the scaled decimal representation; then use the decimal to binary /hex conversion function on a calculator and write to the register. a few examples have been provided in table 3 . table 3. example 20.12 r-values desired output to input clock ratio (output clock/input clock) scaled decimal representation = (output clock/input clock) ? 2 20 hex representation of binary r ud 12.288 mhz/10 mhz=1.2288 1288490 00 13 a9 2a 11.2896 mhz/44.1 khz=256 268435456 10 00 00 00 desired output to input clock ratio (output clock/input clock) scaled decimal representation = (output clock/input clock) ? 2 12 hex representation of binary r ud 12.288 mhz/60 hz=204,800 838860800 32 00 00 00 11.2896 mhz/59.97 hz =188254.127... 771088904 2d f5 e2 08
cs2100-cp ds840f1 31 10.package dimensions notes: 1. reference document: jedec mo-187 2. d does not include mold flash or prot rusions which is 0.15 mm max. per side. 3. e1 does not include inter-lead flash or protrusions which is 0.15 mm max per side. 4. dimension b does not include a total allo wable dambar protrusion of 0.08 mm max. 5. exceptions to jedec dimension. thermal characteristics inches millimeters note dim min nom max min nom max a -- -- 0.0433 -- -- 1.10 a1 0 -- 0.0059 0 -- 0.15 a2 0.0295 -- 0.0374 0.75 -- 0.95 b 0.0059 -- 0.0118 0.15 -- 0.30 4, 5 c 0.0031 -- 0.0091 0.08 -- 0.23 d -- 0.1181 bsc -- -- 3.00 bsc -- 2 e -- 0.1929 bsc -- -- 4.90 bsc -- e1 -- 0.1181 bsc -- -- 3.00 bsc -- 3 e -- 0.0197 bsc -- -- 0.50 bsc -- l 0.0157 0.0236 0.0315 0.40 0.60 0.80 l1 -- 0.0374 ref -- -- 0.95 ref -- parameter symbol min typ max units junction to ambient thermal impedance jedec 2-layer jedec 4-layer ja ja - - 170 100 - - c/w c/w 10l msop (3 mm body) package drawing ( note 1 ) e n 1 23 e b a1 a2 a d seating plane e1 1 l side view end view top view l1 c
cs2100-cp 32 ds840f1 11.ordering information 12.references 1. audio engineering society aes-12id-2006: ?aes information document for digital audio measurements - jitter performance specifications,? may 2007. 2. philips semiconductor, ? the i2c-bus specification: version 2 ,? dec. 1998. http://www.semicondu ctors.philips.com 13.revision history product description package pb-free grade temp range container order# cs2100-cp clocking device 10l-msop yes commercial -10 to +70c rail cs2100cp-czz cs2100-cp clocking device 10l-msop yes -10 to +70c tape and reel cs2100cp-czzr cdk2000 evaluation platform - yes - - - CDK2000-CLK release changes f1 updated period jitter specification in ?ac electrical characteristics? on page 7 . updated crystal and ref clock frequency specifications in ?ac electrical characteristics? on page 7 . added ?pll performance plots? section on page 8 . updated ?internal timing reference clock divider? on page 13 and added figure 10 on page 13 . updated use conditions for ?clk_in skipping mode? section on page 14 and page 28 . updated figure 12 on page 15 . removed fsdetect and auto r-mod features per er758rev2. contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual propert y rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semi conductor products may involve potential risks of death, per sonal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not designed, au thorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life su pport products or other crit- ical applications. inclus ion of cirrus products in such appl ications is understood to be full y at the customer?s risk and cir- rus disclaims and makes no warranty, expres s, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or custom- er?s customer uses or permits the use of cirrus products in cr itical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any a nd all liability, including at- torneys? fees and costs, that may result fr om or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. i2c is a trademark of philips semiconductor. spi is a trademark of motorola, inc.

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